Dynamic memory with logic-in-refresh

The invention is a dynamic storage device requiring periodic refresh, and including logical operation circuitry within the refresh circuitry. The individual storage positions of the storage device are periodically read by a refresh amplifier, and then a logical operation is performed on the refresh data before application to the write amplifier. This allows implementation of associative data base searching by cyclically executing a data compare operation within the refresh circuitry.Board of Regents, University of Texas Syste

System and method for searching a data base using a content-searchable memory

" A dynamic storage device requires periodic refresh and includes logical operation circuitry within the refresh circuitry. The individual storage positions of the storage device are periodically read by a refresh amplifier, and then a logical operation is performed on the refresh data before the data re applied to the write amplifier. That operation allows implementation of associative database searching by cyclically executing ""data compare"" and other logical operations within the refresh circuitry. A system of content searching may be implemented in any storage device, dynamic or not, in which a comparand may be matched with any of a plurality of subunits of a word, and a storage bit is used to identify any words in which a mismatch occurs. Upon recognizing a match, the device can be commanded (a) to output the word or a selected portion (which may be different than the matched portion), (b) to move a selected portion of the word to a different location in the word, or (c) to alter the bits of the word or a selected portion. Arithmetical operations may be implemented through such alterations after matching. Off-chip storage systems of use with such devices are also disclosed. "Board of Regents, University of Texas Syste

Synchronization circuit for parallel processing

An apparatus and method for synchronizing parallel processors utilizing a lookahead synchronization circuit is provided by the present invention. A five gate logic circuit is formed as a cell and this cell can serve as a node in a tree logic operation circuit. The tree is capable of realizing a variety of fetch-and-operation, priority and operation-and-broadcast primitives and the cell can serve in a carry circuit of a binary adder. The tree may be pruned at any point and the circuit will continue to function for those nodes remaining in the tree. Processing elements are attached to leaf nodes of the tree. The present invention is capable of realizing the fetch-and-exclusive-OR, fetch-and-add, fetch-and-AND, fetch-and-OR, fixed priority schema, round-robin priority schema, hogging priority schema, swap, data exchange, broadcast, shift-function, broadcast-from-the-root, AND-and-broadcast, OR-and-broadcast, minimum-and-broadcast, maximum-and-broadcast, exclusive-OR-and-broadcast, fetch-and-minimum, and fetch-and-maximum primitives. The circuit affords significant power in synchronizing parallel processors utilizing simple cells configured in a tree structure.Board of Regents, University of Texas Syste

Parallel associative processor formed from modified dram

A parallel associative processor is formed from a DRAM circuit whose storage positions are organized into words, which are further subdivided into columns. Each column is associated with a sense amplifier, which is used to perform data refreshing. Comparators are coupled to the sense amplifiers to permit logical operations, including comparisions with external data placed on a bus, to be performed on data addressed and read from the storage positions, including during refresh operations. A latch or flip-flop with control inputs is associated with each word, to hold a match or mismatch signal identifying, in parallel for each word, the results of the logical operations.Board of Regents, University of Texas Syste

Apparatus and method for in-parallel scan-line graphics rendering using content-searchable memories

Less-expensive, faster graphics display can be achieved by an in-parallel scan-line rendering system using a content-searchable memory based on a modified DRAM requiring periodic refresh that includes logical operation circuitry within the refresh circuitry. Data at individual storage locations of the DRAM are periodically read by a refresh amplifier, then a logical operation is performed on the refresh data before application to the write amplifier, allowing searching by data compare and mathematical operations. The data words of the content-searchable memory are loaded with data defining the multi-axis location of each of the vertices of a polygonal facet of an object in the scene and display information concerning the facet, such as color or texture. Data representing out-of-view objects can be culled, and the remaining objects projected onto a viewport, all through in-parallel manipulations in the content-searchable memory. For each span along the scan line, a span processor selects the facet closest to the viewport, and data from the selected facet is applied to an electronic display.Board of Regents, University of Texas Syste